It is forecasted in the International Technology Roadmap for Semiconductors (ITRS) that in order to follow the “Moore's law”, obtain better short-channel effect and improve the control of the current leakage from the gate electrode to the channel, new transistor structures, that is, FinFETs (Fin Field Effect Transistors) will be proposed. However, since the width of the fin of a FinFET at 22 nm node dimensions and beyond is approximately 10˜15 nm, which exceeds the resolution limit of the existing immersion lithography equipment, the formation of the fin-like active region is a challenging process. Therefore, the sidewall self-aligned double patterning technology is used for the formation of fin-like active regions. The sidewall self-aligned double patterning technology involves firstly performing immersion lithography and etching processes on a wafer deposited with various mask materials so as to form a sacrificial core pattern, secondly performing an atomic layer deposition (ALD) process to deposit a layer of sidewall material on the sacrificial core pattern, and then using anisotropic dry etching to form sidewalls followed by removing the sacrificial core pattern so as to form hard mask patterns for the fins at desired half pitch, wherein the width of the hard mask is determined by the thickness of the ALD layer; after that, performing lithography and etching processes of line-end cuts for the fins and then using the hard mask patterns as a protection layer and continuing etching to form the fins of the FinFETs.
FIGS. 1A to 1O illustrate the conventional method of forming fin structures and line-end cuts using sidewall self-aligned double patterning technology.
Firstly, as shown in FIG. 1A, on a silicon substrate 101 of a semiconductor active device, a SiO2 insulating layer 102, a SiN layer 103, a first amorphous carbon layer 104, a SiN etch stop layer 105, a second amorphous carbon layer 106 and a nitrogen-free anti-reflection layer 107 are deposited successively from bottom to top. Wherein, the SiN layer 103 is used as a hard mask to form the final fin structures.
Then, as shown in FIG. 1B, an organic anti-reflection layer 108 and a photoresist 109 are spin coated on the top of the layer 107 and then a lithography process is performed to define a sacrificial core pattern.
Afterwards, as shown in FIG. 1C, the photoresist 109 is used as a hard mask to dry etch the second amorphous carbon layer 106 so as to form the sacrificial core pattern in the second amorphous carbon layer 106, thus the amorphous carbon sacrificial core pattern and the nitrogen-free anti-reflection layer 107 on its top are formed. Due to the process limitation, the amorphous carbon sacrificial core pattern does not have completely vertical sidewall profile, and etching damages may occur near the top of the second amorphous carbon layer 106, which may lead to profile variations of the subsequent formed sidewall hard mask adjacent to the second amorphous carbon layer 106 and affect the definition of the subsequent pattern to be formed.
After a wet clean process, as shown in FIG. 1D, a SiO2 hard mask layer 110 is formed on the amorphous carbon sacrificial core pattern and the nitrogen-free anti-reflection layer 107.
As shown is FIG. 1E, anisotropic dry etching is performed to the SiO2 hard mask layer 110 and is stopped on the SiN etch stop layer so as to form SiO2 sidewalls 110.
Then, as shown in FIG. 1F, the nitrogen-free anti-reflection layer 107 of the sacrificial core pattern is removed by plasma dry etching to expose the sacrificial core pattern 106.
As shown in FIG. 1G, the amorphous carbon of the sacrificial core pattern is removed by a dry stripping process.
As shown in FIG. 1H, dry etching is performed using the SiO2 sidewalls 110 as a mask to remove the SiN etch stop layer 105, the first amorphous carbon layer 104 and the bottom SiN layer 103 below the SiO2 sidewalls 110 and is stopped on the SiO2 insulating layer 102, so as to form SiN hard mask lines 111 at half pitches.
After necessary wet clean, as shown in FIG. 1I, a line-end cutting process for the fin lines is performed which involves spin coating a spin-on-carbon layer 112, an anti-reflection layer 113 and a photoresist layer 114 on the SiN hard mask lines 111 and then performing exposure and development to form the required line-end cut pattern.
As shown in FIG. 1J, dry etching is performed using the photoresist layer 114 as a mask to the anti-reflection layer 113, the spin-on-carbon layer 112 and the SiN hard mask and is stopped on the SiO2 insulating layer 102. Then, the spin-on-carbon layer 112 on the SiN hard mask 111 is removed by a dry stripping process to expose the SiN hard mask 111 completely.
After that, as shown in FIG. 1K, the SiN hard mask 111 is used as a hard mask to etch the SiO2 insulating layer 102 and the silicon substrate 101 to form the fin structures 115.
FIG. 1K is a desired result illustrating an extremely flat bottom surface of the line-end cuts after the formation of the fin structures. However, it is not so in the actual process. As shown in FIG. 1L-1M, when the line-end cutting process for the fin structures is performed, the etching rate of the SiN hard mask 111 and that of the spin-on-carbon layer 112 are different, resulting in non-flat etch front at the bottom of the line-end cuts. If the etching rate of the spin-on-carbon layer is faster, silicon protrusions 116 will be formed as shown in FIG. 1L. Such silicon protrusions 116 will become silicon cones 117 as shown in FIG. 1M after etching the silicon substrate to form the fin structures, which finally affects the device electrical performance.
FIGS. 1N to 1O are SEM images corresponding to the actual process steps as shown in FIG. 1L to 1M. FIG. 1N shows the structure after etching the SiN hard mask 111 in which the silicon protrusions 116 can be clearly find out. FIG. 1O illustrates the line-end cut structure when the mask layers on the remained SiN hard mask 111 are removed and the fin structures are formed, wherein the silicon cones 117 can be clearly find out.
From above, one defect of the conventional line-end cutting method for fins is the formation of silicon protrusions and silicon cones during etching which results in the decrease of device electrical performance; another defect is that, since the fins to be formed are protected by the SiN hard mask during etching the silicon substrate, the SiN hard mask should be thick enough to ensure the formation of the fins. However, a too thick SiN hard mask may cause the fins to be formed having a high aspect ratio, thereby affecting the filling ability of the silicon oxide of the shallow trench isolations. While if the thickness of the SiN hard mask is reduced, the etching selectivity to the SiN hard mask should be considered during the etching process for fin formation, which increases the complexity of the etching process for forming fins.
Furthermore, the above mentioned conventional line-end cutting method also affects the alignment in the lithography process for the line-end cuts. In the conventional method, the pattern of the SiN hard mask is formed firstly by etching and the step height of the pattern is determined by the thickness of the SiN hard mask. Since lithographic alignment becomes more difficult due to the fact that lithography alignment marks are cut into segments in the sidewall self-aligned double patterning technology, it is required to increase the step height of the alignment marks, that is, the thickness of the SiN hard mask, and this may also cause the above mentioned conflict.